Frequency synthesizers may be used to generate high frequency clock signals in response to a lower frequency reference clock signal. For example, FIG. 1 shows a block diagram of a phase-locked loop (PLL) configured as a fractional-N frequency synthesizer 100. Synthesizer 100 includes a phase and frequency detector (PFD) 102, a charge pump 104, a loop filter 106, a voltage-controlled oscillator (VCO) 108, a frequency divider 110, and a sigma-delta modulator (SDM) 112. The PFD 102 compares the relative timing (e.g., phase difference) between the edges of a reference signal (X) and a feedback (FB) signal to generate UP and DN control signals. Charge pump 104 converts the UP and DN control signals to a charge (QC) that is proportional to the phase difference of signals X and FB. The charge generated by the charge pump 104 is filtered (e.g., integrated) by filter 106 and provided as a control voltage VC to the VCO 108. The VCO 108 generates an output signal OUT (e.g., in response to the control voltage VC). The output signal OUT is divided by frequency divider 110, which is modulated by a control signal 111 provided by the SDM 112. Because the control signal 111 provided by the SDM 112 may be different for each reference cycle, the output signal OUT may have a frequency that is a non-integer multiple of the frequency of the reference signal X.
Noise associated with the SDM 112 may cause degradation of the synthesizer's phase noise, especially when the synthesizer 100 is to lock the output signal OUT at frequencies substantially higher than (e.g., several or more multiples of) the frequency of the reference signal X. It is desirable to reduce the impact of such noise upon performance of the synthesizer 100.